Low-complexity high-speed decoder design for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Complexity Decoder Architecture for Low-Density Parity-Check Codes
Journal of Signal Processing Systems
Decoder design for RS-based LDPC codes
IEEE Transactions on Circuits and Systems II: Express Briefs
A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders
Journal of Signal Processing Systems
An energy efficient layered decoding architecture for LDPC decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes
Journal of Signal Processing Systems
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Factor graphs and the sum-product algorithm
IEEE Transactions on Information Theory
The capacity of low-density parity-check codes under message-passing decoding
IEEE Transactions on Information Theory
A recursive approach to low complexity codes
IEEE Transactions on Information Theory
Quasicyclic low-density parity-check codes from circulant permutation matrices
IEEE Transactions on Information Theory
Efficient Serial Message-Passing Schedules for LDPC Decoding
IEEE Transactions on Information Theory
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Low Density Parity-Check (LDPC) codes achieve the best performance when they are decoded with the sum-product (SP) algorithm. This is a two-phase iterative algorithm where two types of messages are interchanged and updated in each iteration. The group-shuffled or layered decoding schemes applied to the SP algorithm speed up its convergence by modifying its schedule, so they yield a reduction in the number of iterations required to achieve a given performance. However, the two-phase processing is still maintained. In this paper a modification of the group-shuffled scheme suitable for high-rate LDPC codes is proposed. The modification allows the overlapping of the two-phase computation, achieving a convergence speed up close to that of the group-shuffled scheme with higher throughput. Besides, high throughput architectures are presented for the modified algorithm. As an example, the proposed architecture has been implemented for the 2048-bit LDPC code of the IEEE 802.3an standard and it was synthesized in a 90 nm CMOS process achieving a throughput of 22.40 Gbps at 14 iterations with a clock frequency of 306 MHz and a total area of 10.5 mm2. Furthermore, the decoder performs within 0.5 dB of the floating-point 100 iterations sum-product algorithm at a PER of 10驴5.