Turbo codes: principles and applications
Turbo codes: principles and applications
Lattice Basis Reduction: Improved Practical Algorithms and Solving Subset Sum Problems
FCT '91 Proceedings of the 8th International Symposium on Fundamentals of Computation Theory
Reduced-complexity mimo detector with close-to ml error rate performance
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Relaxed K-best MIMO signal detector design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The error probability of the fixed-complexity sphere decoder
IEEE Transactions on Signal Processing
Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector
Proceedings of the Conference on Design, Automation and Test in Europe
Systolic like soft-detection architecture for 4x4 64-QAM MIMO system
Proceedings of the Conference on Design, Automation and Test in Europe
Systolic block Householder transformation for RLS algorithm withtwo-level pipelined implementation
IEEE Transactions on Signal Processing
On the sphere-decoding algorithm I. Expected complexity
IEEE Transactions on Signal Processing - Part I
Bit-interleaved coded modulation
IEEE Transactions on Information Theory
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
Soft-output sphere decoding: algorithms and VLSI implementation
IEEE Journal on Selected Areas in Communications
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Multiple-Input-Multiple-Output communication systems demand fast sphere decoding with high performance. To speed up the computation, we propose a scheme with multiple fixed complexity sphere decoders to construct a parallel soft-output fixed complexity sphere decoder (PFSD). The proposed decoder is highly parallel and has performance comparable to soft-output list fixed complexity sphere decoder (LFSD) and K-best sphere decoder. In addition, we propose a parallel QR decomposition algorithm to lower the preprocessing overhead, and a low complexity LLR algorithm to allow parallel update of LLR values. We demonstrate that the PFSD algorithm can increase the throughput and reduce bit error rate of a soft-output solution in a 4驴脳驴4 16-QAM system, and has superior performance compared to other soft decoders with comparable throughput and computation complexity. The PFSD algorithm has been mapped onto Xilinx XC4VLX160 FPGA. The resulting PFSD decoder can achieve up to 75 Mbps throughput for 4驴脳驴4 64-QAM configuration at 100MHz with low control overhead.