A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
IEEE Transactions on Image Processing
A novel unrestricted center-biased diamond search algorithm for block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Hexagon-based search pattern for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
A novel cross-diamond search algorithm for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Parallel architectures for 3-step hierarchical search block-matching algorithm
IEEE Transactions on Circuits and Systems for Video Technology
A new three-step search algorithm for block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
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Motion estimation is a highly computational demanding operation during video compression process and significantly affects the output quality of an encoded sequence. Special hardware architectures are required to achieve real-time compression performance. Many fast search block matching motion estimation (BMME) algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose three new hardware architectures of fast search block matching motion estimation algorithm using Line Diamond Parallel Search (LDPS) for H.264/AVC video coding system. These architectures use pipeline and parallel processing techniques and present minimum latency, maximum throughput and full utilization of hardware resources. The VHDL code has been tested and can work at high frequency in a Xilinx Virtex-5 FPGA circuit for the three proposed architectures.