Cache write generate for parallel image processing on shared memory architectures

Authors:
C. M. Wittenbrink;A. K. Somani;Chung-Ho Chen
Affiliations:
Dept. of Electr. Eng., Washington Univ., Seattle, WA;-;-
Venue:
IEEE Transactions on Image Processing
Year:
1996

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Achieving Robustness and Minimizing Overhead in Parallel Algorithms Through Overlapped Communication/Computation

The Journal of Supercomputing - Special issue on embedded fault-tolerance systems

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Abstract

We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated