High Performance Array Processor for Video Decoding
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
DCT-domain coder for digital video applications
Journal of Real-Time Image Processing
VLSI implementation of a configurable IP Core for quantized discrete cosine and integer transforms
International Journal of Circuit Theory and Applications
Multimedia Tools and Applications
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The two-dimensional (2-D) discrete cosine transform (DCT) and the subsequent quantization of the transform coefficients are two computationally demanding steps of any DCT-based video encoder. In this paper, we propose an efficient joint implementation of these two steps, where the precision in computing the DCT can be exchanged for a reduction in the computational complexity. First, the quantization is embedded in the DCT, thus eliminating the need to explicitly quantize the transform coefficients. A multiplierless integer implementation of the quantized DCT (QDCT) is then proposed that performs shift and add operations instead of full multiplications. A sequence of multiplierless QDCT algorithms is obtained with increasing precision and number of computations. Finally, further savings in computations are obtained by terminating the DCT computations whenever intermediate results indicate that the transform and quantization steps will likely result in a block of zero values. The proposed algorithms are applied to, and results are presented for, high-quality MPEG-2 and low bit rate H.263 video encoding