A high-performance VLSI architecture for the histogram peak-climbing data clustering algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bandwidth adaptive hardware architecture of K-Means clustering for video analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An analog on-line-learning K-means processor employing fully parallel self-converging circuitry
Analog Integrated Circuits and Signal Processing
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A new adaptive k-means clustering algorithm for real-time video imaging is presented. In the proposed solution, a weighted contribution of both pixel intensity and distance between the pixels is used for cluster identification. The weight adaptation of each parameter reduces the computation complexity and makes it possible to implement the algorithm in hardware. The algorithm is designed for real-time video imaging in a VLSI implementation. It was implemented with 15 kgates and maximum clock rate of 80 MHz. Simulation results prove that a QCIF image could be handled in 15 f/s.