Chaotic dynamics for multi-value content addressable memory
Neurocomputing
Implementation of a single chaotic neuron using an embedded system
MICAI'12 Proceedings of the 11th Mexican international conference on Advances in Computational Intelligence - Volume Part II
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The design of a chaotic neuron model is proposed and implemented in a CMOS very large scale integration (VLSI) chip. The transfer function of the neuron is defined as a piecewise linear (PWL) N-shaped function. In this paper, the new concept of the baseline function is introduced. It is the mapping of the neuron state to the neuron output. It is used to control the chaotic behavior of collective neurons. The chaotic behavior is analyzed and verified by Lyapunov exponents. An analog CMOS chip was designed to implement the theory and it was fabricated through the MOSIS program. The measurement diagnoses of the chip is demonstrated