Hardware implementation of CMAC neural network with reduced storage requirement

Authors:
Jar-Shone Ker;Yau-Hwang Kuo;Rong-Chang Wen;Bin-Da Liu
Affiliations:
Dept. of Electron. Eng., Kao Yuan Jr. Coll. of Technol. & Commerce, Kaohsiung;-;-;-
Venue:
IEEE Transactions on Neural Networks
Year:
1997

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Abstract

The cerebellar model articulation controller (CMAC) neural network has the advantages of fast convergence speed and low computation complexity. However, it suffers from a low storage space utilization rate on weight memory. In this paper, we propose a direct weight address mapping approach, which can reduce the required weight memory size with a utilization rate near 100%. Based on such an address mapping approach, we developed a pipeline architecture to efficiently perform the addressing operations. The proposed direct weight address mapping approach also speeds up the computation for the generation of weight addresses. Besides, a CMAC hardware prototype used for color calibration has been implemented to confirm the proposed approach and architecture