Implementing of neuro-fuzzy system with high-speed, low-power CMOS circuits in current-mode
MINO'10 Proceedings of the 9th WSEAS international conference on Microelectronics, nanoelectronics, optoelectronics
A low-power CMOS analog neuro-fuzzy chip
ICNC'06 Proceedings of the Second international conference on Advances in Natural Computation - Volume Part II
Design of current-mode modular programmable analog CMOS FLC
Journal of Intelligent & Fuzzy Systems: Applications in Engineering and Technology
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This paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input-output delay, and precision, performs as a fully analog implementation. However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core. Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture are smaller than those of its purely analog counterparts simply because most rules are implemented through programming. The paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype. This prototype, called multiplexing fuzzy controller (MFCON), has been realized in a CMOS 0.7 μm standard technology. It has two inputs, implements 64 rules, and features 500 ns of input to output delay with 16-mW of power consumption. Results from the chip in a control application with a dc motor are also provided.