Error Tolerance in Server Class Processors

Authors:
J. A. Rivers;M. S. Gupta; Jeonghee Shin;P. N. Kudva;P. Bose
Affiliations:
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA;-;-;-;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2011

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On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip

ACM Journal on Emerging Technologies in Computing Systems (JETC)

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Abstract

This paper provides: 1) a very brief motivation and technological trend data to show why hard and soft errors are expected to be of increasing concern in the future; 2) a summary review of chip-level error tolerance practices today-with a brief reference to IBM's POWER6 and POWER7 designs; 3) open research challenges and current solution approaches of promise, based on published literature; and 4) concluding remarks.