Leakage Current Reduction in Data Caches on Embedded Systems
IPC '07 Proceedings of the The 2007 International Conference on Intelligent Pervasive Computing
Proceedings of the 45th annual Design Automation Conference
Hybrid cache architecture with disparate memory technologies
Proceedings of the 36th annual international symposium on Computer architecture
Energy reduction for STT-RAM using early write termination
Proceedings of the 2009 International Conference on Computer-Aided Design
Energy- and endurance-aware design of phase change memory caches
Proceedings of the Conference on Design, Automation and Test in Europe
A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM)
Proceedings of the Conference on Design, Automation and Test in Europe
Power and performance of read-write aware hybrid caches with non-volatile memories
Proceedings of the Conference on Design, Automation and Test in Europe
Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM)
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Multi retention level STT-RAM cache designs with a dynamic refresh scheme
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Hi-index | 0.00 |
In the past, the spin-transfer torque RAM (STT-RAM) suffered from the slow write speed and the high write energy consumption. The latest progress in device engineering has dramatically reduced the write time to a few nanoseconds and hence enabled the fast-switching STT-RAM (FS-STT-RAM). However, the enhancement in write performance results in the degradation of read operations, in terms of both speed and data reliability. Our analysis shows that the read performance becomes critical. Based upon the tradeoff among the read latency, read errors, and system performance, we propose a new FS-STT-RAM architecture, which can switch between two operation modes for either high data accuracy or low power consumption with the support of operation system. In the high accuracy mode, FS-STT-RAM applies the rewrite-after-read scheme to eliminate the data disturbances induced by read current. Even so, with enhancement from shadow rewrite buffer and bit invert scheme, it gains an average 19% improvement in energy-delay-product (EDP) compared to a conventional STT-RAM. When an application can afford a very low chance of read disturbance, the proposed FS-STT-RAM can operate in the low power mode and further boost the average EDP improvement to 34%.