Design of a Tri-Modal Multi-Threshold CMOS Switch With Application to Data Retentive Power Gating

Authors:
Ehsan Pakbaznia;Massoud Pedram
Affiliations:
University of Southern California, Los Angeles, U.S.A;University of Southern California, Los Angeles, U.S.A
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

Citing 0
Cited 2

AFReP: application-guided function-level registerfile power-gating for embedded processors

Proceedings of the International Conference on Computer-Aided Design
ARGO: aging-aware GPGPU register file allocation

Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

Quantified Score

Hi-index	0.00

Visualization

Abstract

A tri-modal multi-threshold CMOS (MTCMOS) switch design is presented. Similar to the conventional MTCMOS switches, the tri-modal switch comes in two flavors: header and footer. The tri-modal switch provides three different power modes for the underlying circuit: active, drowsy, and sleep. The ability of data retention in the drowsy mode makes the proposed tri-modal switch an excellent candidate for implementing data-retentive power gating designs. We will see that three different low-power design schemes, namely data-retentive power gating, multi-drowsy mode structures, and on-chip dynamic voltage scaling, are implemented using the proposed tri-modal switch. We show that our proposal introduces superior low-power solutions across various circuit operating modes using a single circuitry.