On the Reliability of Computational Structures Using Majority Logic

  • Authors:

  • Jie Han;Erin R. Boykin;Hao Chen;Jinghang Liang;José A. B. Fortes

  • Affiliations:

  • Department of Electrical and Computer Engineering at the University of Alberta, Edmonton, Canada;Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA;Department of Electrical and Computer Engineering at the University of Alberta, Edmonton, Canada;Department of Electrical and Computer Engineering at the University of Alberta, Edmonton, Canada;Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA

  • Venue:
  • IEEE Transactions on Nanotechnology
  • Year:
  • 2011

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Abstract

The importance of the reliability of majority-based structures stems from their use in both conventional fault-tolerant architectures and emerging nanoelectronic systems. In this paper, analytical models are developed in order to gain a better understanding of the reliability of majority logic in these contexts. A minimally biased input scenario for $N$-input majority gates ( $N$ odd) occurs when only a minimal majority of the inputs are in consensus. In a tree of gates with these inputs, this paper determines 1) that any nonzero error rate of the majority gates and/or of its initial inputs will result in an unreliable output and 2) that the use of majority gates with a larger number of inputs leads to a less reliable structure. These results are extended to $N$-input minority gates for odd $N$. Although these findings are based on tree structures, their implications to circuit design are explored by investigating several fault-tolerant and nanoelectronic architectures. The simulation results show that the increased probability of error in nanoscale devices may impose serious constraints on the reliability of emerging nanoelectronic circuits, as well as their fault-tolerant counterparts. The worst case reliability must be accounted for in a fault-tolerant design to ensure reliable operation.