FPGA based sliding window architecture for RC5 encryption

Authors:
A. Ruhan Bevi;S. S. V. Sheshu;S. Malarvizhi
Affiliations:
SRM University Chennai, India;SRM University Chennai, India;SRM University Chennai, India
Venue:
Proceedings of the International Conference on Advances in Computing, Communications and Informatics
Year:
2012

Citing 3
Cited 0

Observations on Using Genetic Algorithms for Dynamic Load-Balancing

IEEE Transactions on Parallel and Distributed Systems
Hardware Engines for Bus Encryption: A Survey of Existing Techniques

Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
A dual-priority real-time multiprocessor system on FPGA for automotive applications

Proceedings of the conference on Design, automation and test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

In the current scenario, security for the data has more of its concern. Many encryption algorithms have been proposed to satisfy certain levels of security issues and known for their cryptographic strengths. The extensive use of reconfigurable processors like FPGA for cryptographic applications has made the design and testing of hardware logic simple. This paper introduces, a new sliding window based hardware architecture in Xilinx FPGA for RC5 cryptographic algorithm modeled to satisfy the response and waiting time. This is done to provide faster encryption thereby reducing the risk of deadline miss. The performance comparison between implementation of various RC5 architectures based on area and delay are graphed.