Designing with FPGAs and CPLDs
Designing with FPGAs and CPLDs
Digital Design: Principles and Practices
Digital Design: Principles and Practices
Digital Image Processing
Hi-index | 0.00 |
This paper presents an efficient FPGA based architecture for Sobel edge detection algorithm in respect of both time and space complexity. Various edge detection algorithms are typically used in image processing, artificial intelligence etc. In this paper the Sobel edge detection algorithm using hardware description language and its implementation in Field Programmable Gate Array (FPGA) device is presented in an efficient way. Sobel edge detection algorithm is chosen due to its property of less deterioration in high levels of noise. The result shows a significant improvement of time and space complexity over an existing architecture.