Design and implementation of efficient vedic multiplier using reversible logic

  • Authors:

  • P. Saravanan;P. Chandrasekar;Livya Chandran;Nikilla Sriram;P. Kalpana

  • Affiliations:

  • Department of ECE, PSG College of Technology, Coimbatore, Tamil Nadu, India;Department of ECE, PSG College of Technology, Coimbatore, Tamil Nadu, India;Department of ECE, PSG College of Technology, Coimbatore, Tamil Nadu, India;Department of ECE, PSG College of Technology, Coimbatore, Tamil Nadu, India;Department of ECE, PSG College of Technology, Coimbatore, Tamil Nadu, India

  • Venue:
  • VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
  • Year:
  • 2012

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Abstract

Reversible logic is considered as the emerging technologies in the field of optical computing, low power design and Nano electronics. It has been proved that reversible logic ideally dissipates zero power. In Digital Signal Processing (DSP) applications, multiplier plays an important role. Hence in this work, we proposed an efficient multiplier design using Nikhilam sutra of Vedic Mathematics and implemented it in reversible logic. The proposed implementation gives minimum number of ancilla inputs, garbage outputs and quantum cost there by reducing the computation time.