Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Multiple supply voltage based (V dd ) Systems on Chip (SoCs) allow designers to implement large, complex systems for diverse applications. However, the need for level conversion imposes penalties and often results in non-optimal SoCs. Thus, the level converters are overhead for the circuits in which they are being used. If power consumption of the level converters continues to grow, then they will fail to serve the very purpose for which they were built. This paper proposes the power (leakage)-delay optimization of a DC to DC universal voltage level converter (ULC) using a dual-T ox (dual-oxide CMOS or DOXCMOS) technique and exploiting transistor geometry. The proposed ULC is a novel circuit proposed here for the first time and performs level-up, level-down conversion, or blocking of the input signal, based on the requirements. The paper further proposes a novel design methodology accompanied by an optimization algorithm for the parasitic-aware power-delay optimization of the ULC circuit. The entire design has been implemented in 90 nm CMOS up to layout, including DRC/LVS and parasitic (RC) re-simulation, and was subjected to process variation of 10 process parameters. The optimal ULC with 20 transistors yields power savings of 87.5 %, delay improvement of 87.3 % and area savings of 21 % over the baseline design. It is a robust design performing a stable voltage level conversion for voltages as low as 0.6 V (50 % of V dd ) and loads varying from 10 to 200 fF.