The reduceron reconfigured and re-evaluated

  • Authors:

  • Matthew Naylor;Colin Runciman

  • Affiliations:

  • Department of computer science, university of york, york, north yorkshire, uk (e-mail: mfn@cs.york.ac.uk, colin@cs.york.ac.uk);Department of computer science, university of york, york, north yorkshire, uk (e-mail: mfn@cs.york.ac.uk, colin@cs.york.ac.uk)

  • Venue:
  • Journal of Functional Programming
  • Year:
  • 2012

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Abstract

A new version of a special-purpose processor for running lazy functional programs is presented. This processor-the Reduceron-exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.