A low power voltage limiter for a full passive UHF RFID sensor on a 0.35µm CMOS process

  • Authors:

  • E. FernáNdez;A. Beriain;H. Solar;I. Rebollo;A. GarcíA-Alonso;J. Sosa;J.M MonzóN;S. GarcíA-Alonso;J. A. Montiel-Nelson;R. Berenguer

  • Affiliations:

  • Department of Control and Evaluation LORTEK and University of Navarra, San Sebastián, Paseo Mikeletegui 48, 20009 San Sebastian, Spain;Communication IC Design Group (COMMIC) CEIT and University of Navarra, San Sebastián, Spain;Communication IC Design Group (COMMIC) CEIT and University of Navarra, San Sebastián, Spain;FARSENS S.L., San Sebastián, Spain;Communication IC Design Group (COMMIC) CEIT and University of Navarra, San Sebastián, Spain;Department of Electronic Engineering and Automatics, University of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain;Department of Electronic Engineering and Automatics, University of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain;Department of Electronic Engineering and Automatics, University of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain;Department of Electronic Engineering and Automatics, University of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain;Communication IC Design Group (COMMIC) CEIT and University of Navarra, San Sebastián, Spain

  • Venue:
  • Microelectronics Journal
  • Year:
  • 2012

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Abstract

This paper presents a low power voltage limiter design for avoiding possible damages in the analog front-end of a RFID sensor due to voltage surges whenever readers and tags are close. The proposed voltage limiter design takes advantage of the implemented bandgap reference and voltage regulator blocks in order to provide low deviation of the limiting voltage due to temperature variation and process dispersion. The measured limiting voltage is 2.9V with a voltage deviation of only +/-0.065V for the 12 measured dies. The measured current consumption is only 150nA when the reader and the tag are far away, not limiting the sensitivity of the tag due to an undesired consumption in the voltage limiter. The circuit is implemented on a low cost 2P4M 0.35@mm CMOS technology.