An accurate sparse-matrix based framework for statistical static timing analysis

  • Authors:
  • Anand Ramalingam;Ashish Kumar Singh;Sani R. Nassif;Gi-Joon Nam;Michael Orshansky;David Z. Pan

  • Affiliations:
  • Magma Design Automation, Austin, TX 78759, United States;Terra Technology, Schaumburg, IL, 60173, United States;Austin Research Lab, IBM, Austin, TX 78758, United States;Austin Research Lab, IBM, Austin, TX 78758, United States;Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78712, United States;Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78712, United States

  • Venue:
  • Integration, the VLSI Journal
  • Year:
  • 2012

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Abstract

Statistical static timing analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such accuracy requires careful attention to the delay models and to the algorithms applied. In this paper, we propose a new sparse-matrix based framework for accurate path-based SSTA, motivated by the observation that the number of timing paths in practice is sub-quadratic based on a study of industrial circuits and the ISCAS89 benchmarks. Our sparse-matrix based formulation has the following advantages: (a) it places no restrictions on process parameter distributions; (b) it can use an accurate polynomial-based delay model which takes into account slope propagation naturally; (c) it takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. Our experimental results are very promising.