Flexible LDPC decoder architectures

Authors:
Muhammad Awais;Carlo Condo
Affiliations:
Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy;Department of Electronics and Telecommunications, Politecnico di Torino, Torino, Italy
Venue:
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
Year:
2012

Citing 29
Cited 0

Introduction to parallel algorithms and architectures: array, trees, hypercubes

Introduction to parallel algorithms and architectures: array, trees, hypercubes
Networks on Chips: A New SoC Paradigm

Computer
Reliable low-power digital signal processing via reduced precision redundancy

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implementing LDPC Decoding on Network-on-Chip

VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks

Proceedings of the 32nd annual international symposium on Computer Architecture
Interconnection framework for high-throughput, flexible LDPC decoders

Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Low cost LDPC decoder for DVB-S2

Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation

ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Reconfigurable Shuffle Network Design in LDPC Decoders

ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes

VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Low complexity LDPC code decoders for next generation standards

Proceedings of the conference on Design, automation and test in Europe
A Design for Directed Graphs with Minimum Diameter

IEEE Transactions on Computers
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder

Proceedings of the 45th annual Design Automation Conference
A reconfigurable application specific instruction set processor for convolutional and turbo decoding in a SDR environment

Proceedings of the conference on Design, automation and test in Europe
Efficient shuffle network architecture and application for WiMAX LDPC decoders

IEEE Transactions on Circuits and Systems II: Express Briefs
Design of a multimode QC-LDPC decoder based on shift-routing network

IEEE Transactions on Circuits and Systems II: Express Briefs
Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm

DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Flexible LDPC decoder design for multigigabit-per-second applications

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Low-complexity switch network for reconfigurable LDPC decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures

IEEE Transactions on Circuits and Systems Part I: Regular Papers
Multi-Gb/s LDPC code design and implementation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder

DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Factor graphs and the sum-product algorithm

IEEE Transactions on Information Theory
Optimal decoding of linear codes for minimizing symbol error rate (Corresp.)

IEEE Transactions on Information Theory
A recursive approach to low complexity codes

IEEE Transactions on Information Theory
Mapping interleaving laws to parallel turbo and LDPC decoder architectures

IEEE Transactions on Information Theory
LDPC block and convolutional codes based on circulant matrices

IEEE Transactions on Information Theory

Quantified Score

Hi-index	0.00

Visualization

Abstract

Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.