Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality

Authors:
Heechul Yun;Gang Yao;Rodolfo Pellizzoni;Marco Caccamo;Lui Sha
Affiliations:
-;-;-;-;-
Venue:
ECRTS '12 Proceedings of the 2012 24th Euromicro Conference on Real-Time Systems
Year:
2012

Citing 0
Cited 3

Multi-core composability in the face of memory-bus contention

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Scheduling of mixed-criticality applications on resource-sharing multicore systems

Proceedings of the Eleventh ACM International Conference on Embedded Software
Mixed-criticality scheduling on multiprocessors

Real-Time Systems

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Abstract

Shared resource access interference, particularly memory and system bus, is a big challenge in designing predictable real-time systems because its worst case behavior can significantly differ. In this paper, we propose a software based memory throttling mechanism to explicitly control the memory interference. We developed analytic solutions to compute proper throttling parameters that satisfy schedulability of critical tasks while minimize performance impact caused by throttling. We implemented the mechanism in Linux kernel and evaluated isolation guarantee and overall performance impact using a set of synthetic and real applications.