Improved formal worst-case timing analysis of weighted round robin scheduling for ethernet
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
| Hi-index | 0.00 |
Worst case backlog evaluation is a key issue to avoid under or over sizing of output port buffers for store-and-forward switches. Typically, the dimensioning of switches in the context of avionics is at least as important as the upper bounding of the end-to-end delays. This paper presents a new method based on the Trajectory approach for backlog evaluation of output ports of AFDX switches. On an industrial AFDX configuration, this new method leads to an average buffer size reduction of 10\% compared to the existing Network Calculus approach.