Petri nets: an introduction
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Arbiters: an exercise in specifying and decomposing asynchronously communicating components
Science of Computer Programming
CMOS design of the tree arbiter element
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Decomposition in Asynchronous Circuit Design
Concurrency and Hardware Design, Advances in Petri Nets
Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT
Fundamenta Informaticae - Special issue on application of concurrency to system design (ACSD'04)
Gate-level modelling and verification of asynchronous circuits using CSPM and FDR
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
Automated Verification of Asynchronous Circuits Using Circuit Petri Nets
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
Synchronization and Arbitration in Digital Systems
Synchronization and Arbitration in Digital Systems
Covering conditions and algorithms for the synthesis of speed-independent circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A new way of constructing N-way arbiters is proposed. The main idea is to perform arbitrations between all pairs of requests, and then make decision on what grant to issue based on their outcomes. Crucially, all the mutual exclusion elements in such an arbiter work in parallel. This ‘flat’ arbitration is prone to new threats such as formation of cycles (leading to deadlocks), but at the same time opens up new opportunities for designing arbitration structures with different decision policies due to the availability of the global order relation between requests. To facilitate resolution of such cycles and further developments in the context of flat arbitration, the paper presents new theoretical results, including a proof of correctness of a generic structure for the N-way arbiter decision logic. In particular, in some situations a request that lost some pairwise arbitrations has to be granted to avoid a deadlock.