Isolation types and multi-core architectures

  • Authors:
  • Alan Mycroft

  • Affiliations:
  • Computer Laboratory, University of Cambridge, Cambridge, UK

  • Venue:
  • FoVeOOS'11 Proceedings of the 2011 international conference on Formal Verification of Object-Oriented Software
  • Year:
  • 2011

Quantified Score

Hi-index 0.00

Visualization

Abstract

Programs distributed between two or more cores on a multi-core processor are significantly slowed down when both repeatedly access the same cache line--unless both accesses consist of reads. The hardware performs best when programs satisfy a 'memory isolation' property whereby each line of writable memory is available to only one processor at a time. Multi-core memory isolation encapsulates a multiple-reader/single-writer usage, with a cost incurred when changing one writer for another. This tutorial-style work starts with a historical perspective and then shows how existing work on Kilim and its isolation-type system provides a programming-language form to express such memory isolation including ownership transfer.