Application-aware prefetch prioritization in on-chip networks

Authors:
Nachiappan Chidambaram Nachiappan;Asit K. Mishra;Mahmut Kademir;Anand Sivasubramaniam;Onur Mutlu;Chita R. Das
Affiliations:
The Pennsylvania State University, State College, PA, USA;Intel Corp., Hillsboro, OR, USA;The Pennsylvania State University, State College, PA, USA;The Pennsylvania State University, State College, PA, USA;Carnegie Mellon University, Pittsburg, PA, USA;The Pennsylvania State University, State College, PA, USA
Venue:
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Year:
2012

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Abstract

Data prefetching is an effective technique for hiding memory latency. When issued prefetches are inaccurate, performance can degrade. Prior research provided solutions to deal with inaccurate prefetches at the cache and memory levels, but not in the interconnect of a large-scale multiprocessor system. This work introduces application-aware prefetch prioritization techniques to mitigate the negative effects of prefetching in a network-on-chip (NoC) based multicore system. The idea is to rank prefetches from different applications based on their potential utility for the application and propensity to cause interference to other applications. Our evaluation shows that this approach provides significant performance improvements over a baseline that does not distinguish between prefetches from different applications.