3D integration for power-efficient computing
Proceedings of the Conference on Design, Automation and Test in Europe
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With the emergence of many core architectures, the need of on-chip memories such as caches grows faster than the number of cores. Moreover the bandwidth to off-chip memories is saturating. Big memory caches can alleviate the pressure to off-chip accesses. In this paper, we present an adaptive 3Dcache architecture taking advantage of dense vertical connections in stacked chips. Then we propose a dynamically adaptive mechanism to optimize the use of the aforementioned 3D cache architecture according to the workload needs. Finally, we analyze the gain on memory accesses and on software execution time in a realistic model of many core architecture and we study the hardware cost of our proposal, showing that our approach can lead to a 50% reduction of both external memory accesses and application execution time.