Modeling performance through memory-stalls

  • Authors:
  • Roman Iakymchuk;Paolo Bientinesi

  • Affiliations:
  • AICES, RWTH Aachen, Aachen, Germany;AICES, RWTH Aachen, Aachen, Germany

  • Venue:
  • ACM SIGMETRICS Performance Evaluation Review
  • Year:
  • 2012
  • Execution-less performance modeling

    Proceedings of the second international workshop on Performance modeling, benchmarking and simulation of high performance computing systems

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Abstract

We aim at modeling the performance of linear algebra algorithms without executing either them or parts of them. The performance of an algorithm can be expressed in terms of the time spent on CPU execution and on memory-stalls. The main concern of this paper is to build analytical models to accurately predict memory-stalls. The scenario in which data resides in the L2 cache is considered; with this assumption, only L1 cache misses occur. We construct an analytical formula for modeling the L1 cache misses of fundamental linear algebra operations such as those included in the Basic Linear Algebra Subprograms (BLAS) library. The number of cache misses occurring in higher-level algorithms "like a matrix factorization" is then predicted by combining the models for the appropriate BLAS subroutines. As case studies, we consider GER, a BLAS level-2 operation, and the LU factorization. The models are validated on both Intel and AMD processors, attaining remarkably accurate performance predictions.