Multi-rate Polyphase DSP and LMS Calibration Schemes for Oversampled ADCs

Authors:
Subhanshu Gupta;Yi Tang;Jeyanandh Paramesh;David J. Allstot
Affiliations:
Department of Electrical Engineering, Univ. of Washington, Seattle, USA 98195 and RFIC Engineering, Maxlinear Inc., Irvine, USA 92612;Qualcomm Inc., San Diego, USA 92121;Department of Electrical and Computer Engineering, Carnegie Mellon Univ., Pittsburgh, USA 15213;Department of Electrical Engineering, Univ. of Washington, Seattle, USA 98195
Venue:
Journal of Signal Processing Systems
Year:
2012

Citing 3
Cited 0

Discrete-time signal processing

Discrete-time signal processing
Adaptive Filtering: Algorithms and Practical Implementation

Adaptive Filtering: Algorithms and Practical Implementation
Digitally Assisted Analog Circuits

IEEE Micro

Quantified Score

Hi-index	0.00

Visualization

Abstract

A scaling-friendly approach for the low-power calibration of oversampled analog-to-digital (A/D) systems is presented. A 22-dB amplifier relaxes the design constraints of the analog front-end (AFE). The integrator non-idealities in the AFE of the sigma-delta (ΣΔ) ADC are calibrated using a multi-rate polyphase least-mean squares (LMS) algorithm. The proposed half- (f s/2) and quarter-rate (f s/4) LMS calibration schemes reduce computational complexity and achieve more than 2.5脳 savings in digital power consumption for low-OSR (over-sampling ratio) ΔΣ ADCs, which require higher adaptive filter orders and sampling frequencies. The proposed scheme can have further applications in serial-link I/O and sub-band echo cancellation architectures.