Octrees for faster isosurface generation
ACM Transactions on Graphics (TOG)
Optimal isosurface extraction from irregular volume data
Proceedings of the 1996 symposium on Volume visualization
Fast isocontouring for improved interactivity
Proceedings of the 1996 symposium on Volume visualization
I/O optimal isosurface extraction (extended abstract)
VIS '97 Proceedings of the 8th conference on Visualization '97
Interactive out-of-core isosurface extraction
Proceedings of the conference on Visualization '98
External memory techniques for isosurface extraction in scientific visualization
External memory algorithms
Global static indexing for real-time exploration of very large regular grids
Proceedings of the 2001 ACM/IEEE conference on Supercomputing
FOCS '99 Proceedings of the 40th Annual Symposium on Foundations of Computer Science
Effectively sharing a cache among threads
Proceedings of the sixteenth annual ACM symposium on Parallelism in algorithms and architectures
A Portable Programming Interface for Performance Evaluation on Modern Processors
International Journal of High Performance Computing Applications
ACM SIGGRAPH 2005 Papers
Faster Isosurface Ray Tracing Using Implicit KD-Trees
IEEE Transactions on Visualization and Computer Graphics
An efficient and scalable parallel algorithm for out-of-core isosurface extraction and rendering
Journal of Parallel and Distributed Computing
Scheduling threads for constructive cache sharing on CMPs
Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures
Binary Mesh Partitioning for Cache-Efficient Visualization
IEEE Transactions on Visualization and Computer Graphics
Case study of multithreaded in-core isosurface extraction algorithms
EG PGV'04 Proceedings of the 5th Eurographics conference on Parallel Graphics and Visualization
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This paper proposes to revisit isosurface extraction algorithms taking into consideration two specific aspects of recent multicore architectures: their intrinsic parallelism associated with the presence of multiple computing cores and their cache hierarchy that often includes private caches as well as caches shared between all cores. Taking advantage of these shared caches require adapting the parallelization scheme to make the core collaborate on cache usage and not compete for it, which can impair performance. We propose to have cores working on independent but close data sets that can all fit in the shared cache. We propose two shared cache aware parallel isosurface algorithms, one based on marching tetrahedra, and one using a min-max tree as acceleration data structure. We theoretically prove that in both cases the number of cache misses is the same as for the sequential algorithm for the same cache size. The algorithms are based on the FastCOL cache-oblivious data layout for irregular meshes. The CO layout also enables to build a very compact min-max tree that leads to a reduced number of cache misses. Experiments confirm the interest of these shared cache aware isosurface algorithms, the performance gain increasing as the shared cache size to core number ratio decreases.