High Performance Fault-Tolerant Digital Neural Networks
IEEE Transactions on Computers
A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant
IEICE - Transactions on Information and Systems
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A digital multilayer perceptron (DMLP) which is tolerant to simultaneous weight and neuron faults is implemented in an FPGA, where the weight faults are assumed to be between the hidden and output layers and the neuron faults are assumed to be in the hidden and output layers. In the implementation, a multilayer perceptron (MLP) trained by the deep learning method [1] is used to cope with the weight faults and the neuron faults in the hidden layer, and an error detecting and correcting code SECDED is used to cope with the neuron faults in the output layer. The implementation process named ''FTDMLP-gene'' is proposed which consists of three parts; the deep learning method, the VHDL source file generator and the outline of VHDL notation which describes an FTDMLP (fault-tolerant DMLP). The fault-tolerant ability of the FTDMLP implemented is shown. Further, The FTDMLP and the corresponding non-fault tolerant DMLP are compared in terms of hardware size, computing speed and electricity consumption. This paper is the extension of [2,3].