Circuit and system design for an 860–960 MHz RFID reader front-ends with Tx leakage suppression in 0.18 − µm CMOS technology

  • Authors:

  • Javad Javidan;S. Mojtaba Atarodi;Howard C. Luong

  • Affiliations:

  • Technical Engineering Department, University of Mohaghegh Ardabili, Iran;EE Department, Sharif University of Technology, Iran;EE Department, The Hong Kong University of Science and Technology, Hong Kong

  • Venue:
  • International Journal of Circuit Theory and Applications
  • Year:
  • 2012

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Abstract

This paper presents an RF Front-END for an 860–960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-µm technology. The chip area is 2.65 mm × 1.35 mm including the bonding pads. The PA delivers an output power of 29 dBm and a power-added efficiency of 24% with a power gain of 20 dB, including the losses of the bond-wires. Copyright © 2011 John Wiley & Sons, Ltd.