Stochastic finite elements: a spectral approach
Stochastic finite elements: a spectral approach
Sub-90nm technologies: challenges and opportunities for CAD
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Statistical Gate-Delay Model Considering Intra-Gate Variability
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Proceedings of the 42nd annual Design Automation Conference
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Stochastic analysis of interconnect performance in the presence of process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A framework for statistical timing analysis using non-linear delay and slew models
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a framework for estimating the timing yield of sequential networks in the presence of process variations. We present an accurate method for characterizing various parameters such as setup time, hold time, clock to output delay etc. of sequential elements in the network. Using these models and the models of interconnects gate delays, and clock skews, we perform statistical timing analysis of combinational blocks in the circuit. The result of the timing analysis is a set of constraints involving random process variables that the network has to satisfy together in order to work correctly. We compute the joint yield of all the constraints to estimate the yield of the entire network. The proposed method provides a speedup of up to 400× compared to 10000 Monte Carlo simulations with an average error of less than 1% and 5% in mean and standard deviation respectively.