A bipartition-codec architecture to reduce power in pipelined circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Decoding of Canonical Huffman Codes with Look-Up Tables
DCC '00 Proceedings of the Conference on Data Compression
High speed pattern matching for a fast Huffman decoder
IEEE Transactions on Consumer Electronics
A bipartition-codec architecture to reduce power in pipelined circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An entropy coding system for digital HDTV applications
IEEE Transactions on Circuits and Systems for Video Technology
Designing high-throughput VLC decoder. I. Concurrent VLSI architectures
IEEE Transactions on Circuits and Systems for Video Technology
FPGA based implementation of baseline JPEG decoder
Proceedings of the 7th International Conference on Frontiers of Information Technology
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JPEG codec in portable device has become a popular technique nowadays. Because the portable device is battery powered, reducing power dissipation is practical. In this paper, a low power design technique for implementing JPEG Huffman decoder is presented, in which the Huffman table is divided into two partitions. As the main contribution, we propose a low power Huffman decoder with bipartition lookup table to reduce the power consumption in JPEG. Experimental results of the gate level simulation show that the proposed method can reduce the power consumption by 15% on average compared to general Huffman decoder.