Rewriting as a unified model of concurrency
CONCUR '90 Proceedings on Theories of concurrency : unification and extension: unification and extension
Executable formal models of distributed transaction systems based on event processing
Executable formal models of distributed transaction systems based on event processing
A Classification and Comparison Framework for Software Architecture Description Languages
IEEE Transactions on Software Engineering
Rewriting logic: roadmap and bibliography
Theoretical Computer Science - Rewriting logic and its applications
Conceptual Modeling of Complex Systems Using an RM-ODP Based Ontology
EDOC '01 Proceedings of the 5th IEEE International Conference on Enterprise Distributed Object Computing
Rewriting Logic as a Semantic Framework for Concurrency: a Progress Report
CONCUR '96 Proceedings of the 7th International Conference on Concurrency Theory
LfP: A Specification Language for Rapid Prototyping of Concurrent Systems
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
A formal approach to software architecture
A formal approach to software architecture
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
Graph-Based Design and Analysis of Dynamic Software Architectures
Concurrency, Graphs and Models
Hierarchical Design Rewriting with Maude
Electronic Notes in Theoretical Computer Science (ENTCS)
A classification and comparison of model checking software architecture techniques
Journal of Systems and Software
A tile logic-based semantics for mobile software architectures
International Journal of Critical Computer-Based Systems
Heuristics to verify LTL properties of hierarchical systems
VECoS'08 Proceedings of the Second international conference on Verification and Evaluation of Computer and Communication Systems
A tile logic based semantics for mobile software architectures
VECoS'10 Proceedings of the Fourth international conference on Verification and Evaluation of Computer and Communication Systems
On the use of real-time maude for architecture description and verification: a case study
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
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Software architecture description languages allow software designers to focus on high level aspects of an application by abstracting from details. In general, a system's architecture is specified in a hierarchical way. In fact, hierarchical components hide, at each level, the complexity of the sub-entities composing the system. As rewriting logic is a natural semantic framework for representing concurrency, parallelism, communication and interaction, it can be used for systems specification and verification. In this paper, we show how we can take advantage of hierarchical modeling of software systems specified with Lf P, to prototype model checking process using Maude system. This approach allows us to hide and show, freely and easily, encapsulated details by moving between hierarchical levels. Thus, state explosion problem is mastered and reduced. In addition, system's maintainability and error detection become easier and faster.