Power efficiency evaluation of block ciphers on GPU-integrated multicore processor

  • Authors:
  • Naoki Nishikawa;Keisuke Iwai;Takakazu Kurokawa

  • Affiliations:
  • Departmemt of Computer Science and Engineering, National Defense Academy of Japan, Yokosuka-shi, Kanagawa-ken, Japan;Departmemt of Computer Science and Engineering, National Defense Academy of Japan, Yokosuka-shi, Kanagawa-ken, Japan;Departmemt of Computer Science and Engineering, National Defense Academy of Japan, Yokosuka-shi, Kanagawa-ken, Japan

  • Venue:
  • ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
  • Year:
  • 2012

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Abstract

Computer systems with discrete GPUs are expected to become the standard methodology for high-speed encryption processing, but they require large amounts of power consumption and are inapplicable to embedded devices. Therefore, we have specifically examined a new heterogeneous multicore processor with CPU---GPU integration architecture. We first implemented three 128-bit block ciphers (AES, Camellia, and SC2000) from several symmetric block ciphers in an e-government recommended ciphers list by CRYPTREC in Japan using OpenCL on AMD E-350 APU with CPU---GPU integration architecture and two traditional systems with discrete GPUs. Then we evaluated their respective power efficiencies. Result showed that performance per watt of AES-128 on the APU including 80 cores were 743.0 Mbps/W and 44.0 % increases compared with those on a system equipped with a discrete AMD Radeon HD 6770 including 800 cores. This paper is the first to describe a study to evaluate the per-watt performance of block ciphers on GPUs.