A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V
IEEE Transactions on Circuits and Systems II: Express Briefs
Class-D audio amplifiers in mobile applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009
A switching-based phase noise model for CMOS ring oscillators based on multiple thresholds crossing
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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This paper presents the design and implementation of a novel pulse width modulation (PWM) chip. With low-power, high-performance, small area, and high speed, these circuits are employed in portable computer systems, such as the power circuits, electronic circuits, video and music amplifiers circuits, communications and control circuits, wireless communication and high-frequency circuit systems. This PWM chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 3.0268 mW, and the chip area size is 1.016 mm ×1.016 mm. Finally, the PWM chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, communications control, etc.