Quantitative synthesis for concurrent programs
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Theoretical Computer Science
Synthesis from incompatible specifications
Proceedings of the tenth ACM international conference on Embedded software
Synthesis from LTL specifications with mean-payoff objectives
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
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Formal verification aims to improve the quality of hardware and software by detecting errors before they do harm. At the basis of formal verification lies the logical notion of correctness, which purports to capture whether or not a circuit or program behaves as desired. We suggest that the boolean partition into correct and incorrect systems falls short of the practical need to assess the behavior of hardware and software in a more nuanced fashion against multiple criteria.