A new technique for characterization of digital-to-analog converters in high-speed systems
Proceedings of the conference on Design, automation and test in Europe
Techniques for high-speed implementation of nonlinear cancellation
IEEE Journal on Selected Areas in Communications
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This paper presents a compact, low power 12.5Gb/s backplane receiver in a 90nm CMOS technology. The receiver incorporates an analog equalizer, which is designed using active inductor circuit, and a 1-tap speculative decision-feedback- equalizer (DFE). The proposed active inductor circuit provides wider tuning range and higher inductive impedance with respect to the previous reported topologies, using negative impedance implemented by a cross coupled transistor pair, at the output nodes of active inductor circuit. The DFE is designed in half rate architecture utilizing an improved front end sample and hold to speculate the first feedback tap while consuming low power and imposing small capacitive load on the analog equalizer block. The input capacitance of the DFE block is alleviated more by changing the place of multiplexer in the DFE architecture. Furthermore power consumption reduction in DFE architecture is achieved by using a novel high speed slicer with rail-to-rail swing in the output to avoid implementing latches and MUXs in the next stages in CML topology. The receiver consumes 6.6mW from a 1.2V supply while delivering 12.5Gb/s data over 5'' NELCO 4000-6 channel in the presence of two aggressor far-end-crosstalk (FEXT) signals.