Cyfield-RISP: generating dynamic instruction set processors for reconfigurable hardware using OpenCL

Authors:
Jörn Hoffmann;Frank Güttler;Karim El-Laithy;Martin Bogdan
Affiliations:
Faculty of Mathematics and Computer Science, Dept. of Computer Engineering, Universität Leipzig, Germany;Faculty of Mathematics and Computer Science, Dept. of Computer Engineering, Universität Leipzig, Germany;Faculty of Mathematics and Computer Science, Dept. of Computer Engineering, Universität Leipzig, Germany;Faculty of Mathematics and Computer Science, Dept. of Computer Engineering, Universität Leipzig, Germany
Venue:
ICANN'12 Proceedings of the 22nd international conference on Artificial Neural Networks and Machine Learning - Volume Part I
Year:
2012

Citing 8
Cited 0

Reconfigurable Instruction Set Processors: A Survey

RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
A quantitative analysis of the speedup factors of FPGAs over processors

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation

Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Mitrion-C Application Development on SGI Altix 350/RC100

FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Unleash the System On Chip using FPGAs and Handel C

Unleash the System On Chip using FPGAs and Handel C
Simulating biological-inspired spiking neural networks with OpenCL

ICANN'10 Proceedings of the 20th international conference on Artificial neural networks: Part I
OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices

FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Synthesis of Platform Architectures from OpenCL Programs

FCCM '11 Proceedings of the 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this work a novel approach to automatically generate hardware is introduced that allows accelerated simulation of artificial neural networks (ANN) on field-programming gate arrays (FPGAs). A compiler architecture has been designed that primarily aims at reducing the development effort for non-hardware developers. This is done by implementing automatic generation of accordingly adjusted hardware processors. Deduced from high-level OpenCL source code, the processors are able to spatially map ANNs in a massive parallel fashion.