UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs

Authors:
Martin Danek;Leos Kafka;Luks Kohout;Jaroslav Skora;Roman Bartosinski
Affiliations:
-;-;-;-;-
Venue:
UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs
Year:
2012

Citing 0
Cited 1

On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches

ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers

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Abstract

This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs.