ACM Computing Surveys (CSUR)
An axiomatic basis for computer programming
Communications of the ACM
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
On Formalism in Specifications
IEEE Software
Verification of UML/OCL Class Diagrams using Constraint Programming
ICSTW '08 Proceedings of the 2008 IEEE International Conference on Software Testing Verification and Validation Workshop
Formal Verification of Avionics Software Products
FM '09 Proceedings of the 2nd World Congress on Formal Methods
Verifying UML/OCL models using Boolean satisfiability
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling languages for real-time and embedded systems: requirements and standards-based solutions
MBEERTS'07 Proceedings of the 2007 International Dagstuhl conference on Model-based engineering of embedded real-time systems
| Hi-index | 0.00 |
In a software development cycle, it is often more than half of the development time that is dedicated to verification activities. Formal methods offer new possibilities for verification. In the specification phase, simulation or model-checking allow users to detect errors in models. In the implementation phase, analysis techniques, like static analysis, make the verification tasks more exhaustive and more automatic. In that context, we propose to take advantage of these methods to improve embedded software development processes based on the V-model.