Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study

  • Authors:

  • Rosilde Corvino;Erkan Diken;Abdoulaye Gamatie;Lech Jozwiak

  • Affiliations:

  • -;-;-;-

  • Venue:
  • DSD '12 Proceedings of the 2012 15th Euromicro Conference on Digital System Design
  • Year:
  • 2012

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Abstract

In this paper, we present a method for the design of MPSoCs for complex data-intensive applications. This method aims at a blend exploration of the communication, the memory system architecture and the computation resource parallelism. The proposed method is exemplified on a JPEG Encoder case study by describing all the design steps. Our method allows for a JPEG encoder implementation having a throughput increase of 84% and an increase of the achievable FPGA maximum frequency fmax of 64% with an area overhead of 6 with respect to a reference solution. Our method is also assessed with additional explorations of applications from different domains.