Scrubbing unit repositioning for fast error repair in FPGAs
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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Evaluating the resilience of a given circuit against adverse effects, such as radiation-induced single event upsets, is a complex and frequently time-demanding task. For Field Programmable Gate Arrays (FPGAs), this task has the additional complexity of accounting for faults affecting the configuration memory. For this reason, several works propose techniques to inject and evaluate faults affecting configuration bits. In this work, we propose a novel platform which requires a single FPGA to perform the fault injection, to apply input vectors and to evaluate the correctness of the outputs. It can evaluate complex fault models, such as multiple bit errors that are caused by a single bit flip. Furthermore, it occupies a small portion of the device resources and works at a very high speed, being able to inject and remove a fault in under 10μ8.