Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design

Authors:
Sunil P. Khatri
Affiliations:
Texas A&M University, College Station, TX 77843
Venue:
ICCD '12 Proceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)
Year:
2012

Citing 0
Cited 2

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Exploring topologies for source-synchronous ring-based network-on-chip

Proceedings of the Conference on Design, Automation and Test in Europe

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Abstract

Recently, a new source-synchronous ring-based NoC architecture has been proposed, which runs significantly faster than the PEs and offers a high bandwidth and low contention free latency. Architectural simulations show that the original ring-based NoC design suffers from deadlock. In this paper, we explore the architectural aspects of the fast ring-based NoC after redesigning the routers used in the previous authors' work to avoid deadlock. Architectural results obtained on synthetic traffic demonstrate that the modified ring-based NoC has up to 3.5脳 lower latency and up to 2.9脳 higher maximum sustained injection rate compared with a state of the art mesh-based NoC.