RFiof: an RF approach to I/O-pin and memory controller scalability for off-chip memories
Proceedings of the ACM International Conference on Computing Frontiers
| Hi-index | 0.00 |
Off-chip memory parallelism can be improved by having multiple memory controllers (MCs). However, MCs scalability is limited by the number and area of I/O pads/pins allocated to them, besides power. In order to address the scalability of MCs and I/O pads in a multi-chip (MCP) flip-chip package, we propose RFiop — a scalable memory organization based on wired-RF, which replaces the traditional MC-DRAM, mostly composed by MC, and I/O pad/pin related structures with RF-designed RFMCs — MCs coupled to RF transmitters (TX) / receivers (RX), RF coplanar waveguides (CPW) — defined as RFpads, and off-die ranks placed on a coplanar fashion. RFiop explores the on-package area to fit off-die ranks, which are connected to the RFMCs via CPWs. Configuring RFiop with off-die lower data-rate-DDR3 ranks, RFiop scales bandwidth for 16 out-of-order (OOO) cores, using 16 RFMCs with about 4 RFpads per RFMC. RFiop leverages performance and bandwidth by a factor of up to 3.95脳, while reducing latency in up to 47%, assuming an electrical-based solution under I/O pad constraints as baseline. Dedicating the baseline area to placing several RFMCs, RFiop improves bandwidth in up to 2.68脳.