DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function

Authors:
Nagesh B Lakshminarayana;Jaekyu Lee;Hyesoon Kim;Jinwoo Shin
Affiliations:
Georgia Institute of Technology, Atlanta;Georgia Institute of Technology, Atlanta;Georgia Institute of Technology, Atlanta;Georgia Institute of Technology, Atlanta
Venue:
IEEE Computer Architecture Letters
Year:
2012

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Abstract

GPGPU architectures (applications) have several different characteristics compared to traditional CPU architectures (applications): highly multithreaded architectures and SIMD-execution behavior are the two important characteristics of GPGPU computing. In this paper, we propose a potential function that models the DRAM behavior in GPGPU architectures and a DRAM scheduling policy Î±-SJF policy to minimize the potential function. The scheduling policy essentially chooses between SJF and FR-FCFS at run-time based on the number of requests from each thread and whether the thread has a row buffer hit.