Impact of compiler optimizations on voltage droops and reliability of an SMT, multi-core processor

Authors:
Youngtaek Kim;Lizy Kurian John;Srilatha Manne;Michael Schulte;Sanjay Pant
Affiliations:
The University of Texas at Austin;The University of Texas at Austin;Advanced Micro Devices, Inc.;Advanced Micro Devices, Inc.;Advanced Micro Devices, Inc.
Venue:
Proceedings of the First International Workshop on Secure and Resilient Architectures and Systems
Year:
2012

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Abstract

In ultra-low power era, one of the most effective ways of reducing power consumption is to lower supply voltage level. When programs execute on processors, voltage fluctuations can occur due to sudden changes in current draw between successive instructions. Such voltage fluctuations can reduce the voltage levels below acceptable levels and cause unreliable operation in microprocessors. Voltage droops due to di/dt effects have been studied in the past, however no prior work studies the effect of compiler optimizations on voltage droops. Past work has studied the impact of compiler optimizations on performance and power, but not reliability. In this paper, we analyze voltage droops with different compiler optimization levels. We also report corresponding performance, power and energy results to put the results into perspective. No clear trends could be observed regarding the effect of compiler optimizations on voltage droops. We conclude that dynamic voltage noise mitigation is necessary because we cannot guarantee voltage noise reduction with static compiler optimization.