Designing a halftoning coprocessor

  • Authors:

  • Anders Kugler;Roger D. Hersch

  • Affiliations:

  • Laboratoire de Systèmes Périphériques, Swiss Federal Institute of Technology, Lausanne, Switzerland;Laboratoire de Systèmes Périphériques, Swiss Federal Institute of Technology, Lausanne, Switzerland

  • Venue:
  • EGGH'93 Proceedings of the Eighth Eurographics conference on Graphics Hardware
  • Year:
  • 1993

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Abstract

Halftoning is a fairly slow process when executed by software on conventional processors. To speed up half toning, a half toning algorithm has been developed and integrated into a dedicated hardware architecture. This paper describes the implementation of the architecture with a XILINX Field Programmable Gate Array (FPGA) and compares its performances with results obtained by a software implementation. A discussion on how to improve the present architecture concludes the paper.