Good Codes Based on Very Sparse Matrices
Proceedings of the 5th IMA Conference on Cryptography and Coding
Proceedings of the 13th international symposium on Low power electronics and design
Factor graphs and the sum-product algorithm
IEEE Transactions on Information Theory
A recursive approach to low complexity codes
IEEE Transactions on Information Theory
Serial Schedules for Belief-Propagation: Analysis of Convergence Time
IEEE Transactions on Information Theory
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Decoding operation reduction algorithms on min-sum layered low-density parity-check (LDPC) decoders are proposed in this paper. Our algorithm freezes selected operations in high reliable nodes to reduce power while preserving error correcting performance. Both memory accesses and active node switching activities can be reduced. A novel node refresh mechanism reactivates frozen nodes to minimize coding gain degradation. We propose three decoding operation reduction algorithm variations to trade-off complexity and operation reduction for LDPC decoders with different degrees of parallelism and memory requirement. Simulation results show that the number of LDPC decoding operations is reduced across all SNR ranges. The decoding convergence speed is not affected. Hardware architecture and FPGA implementation for IEEE 802.16e LDPC codes are presented. Copyright © 2011 John Wiley & Sons, Ltd.